RISC-V is emerging as a crucial player in the evolving landscape of AI hardware, from embedded sensors to data center inference accelerators. Its open, modular Instruction Set Architecture (ISA) allows designers to scale AI computing efficiently while avoiding vendor lock-in. Current applications include fixed-function cores for simple tasks like classification, alongside vector-extended clusters that integrate with Neural Processing Units (NPUs) and Graphics Processing Units (GPUs) to facilitate edge AI and multimodal models.
Recent advancements in RISC-V demonstrate its alignment with a growing array of AI processing requirements. Fixed-function accelerators and Digital Signal Processor (DSP)-class RISC-V cores are increasingly employed for constrained workloads, such as keyword detection and gesture recognition. As AI tasks become more complex, hybrid designs that merge RISC-V CPUs with vector extensions, DSP functions, and NPUs offer enhanced efficiency in handling vision processing and audio intelligence, surpassing general-purpose core capabilities.
The integration of RISC-V vector cores alongside GPUs and NPUs signals a significant architectural shift. These combined systems enable on-device inference and edge AI, capabilities that previously relied on cloud infrastructure. This transition represents a pivotal moment where RISC-V hardware effectively bridges deeply embedded systems with advanced inference workloads. At the cognitive tier, chiplet-based System on Chips (SoCs) and distributed multi-cluster architectures support real-time decision-making, adaptive robotics, and self-optimizing frameworks that require coherent memory across multiple nodes.
Three key approaches are shaping the integration of NPUs directly into the RISC-V architecture. The first, a well-established method, places a discrete NPU alongside a RISC-V CPU, effectively transplanting traditional accelerator models into an open ISA environment. While functional, this design introduces latency and bandwidth limitations due to CPU-to-NPU communication. Another approach, termed “semidynamics,” proposes a RISC-V ISA-only compute engine that merges CPU, vector, and tensor operations into a single compute element, thereby eliminating inter-component communication delays and targeting 8 to 64 trillion operations per second (TOPS) for large language models and edge AI. Academic explorations are delving into dynamic multiply-accumulate (MAC) sharing, where an integrated NPU shares the CPU’s MAC unit when idle, achieving a 1.87× speedup at 93.5% efficiency while reducing power consumption by 70% at lower frequencies—a compact solution for constrained edge applications.
The MIPS S8200 emerges as a commercially significant example, now under GlobalFoundries, which tightly couples RISC-V application cores with AI engines. This integration promotes low-latency data exchange between general-purpose processing and inference, supporting transformer-class models and Convolutional Neural Networks (CNNs) through optimized compilers for frameworks like PyTorch and TensorFlow. This software-first approach allows developers to model and refine inference workloads on virtual platforms prior to silicon availability, paving the way for hardware-software co-design from the outset. ForwardEdge ASIC, a subsidiary of Lockheed Martin, has selected the S8200 for a critical autonomous platform ASIC, with initial silicon reference platforms anticipated in 2027. Academic initiatives like PyTorchSim are further extending this capability by modeling NPUs with custom RISC-V ISAs, providing researchers a unified toolchain to assess NPU architectures before committing to silicon fabrication.
RISC-V vector extensions also facilitate connections across various memory hierarchies, ranging from SRAM-based embedded implementations to pooled memory in semi-cognitive systems. As intelligence demands increase, there is a corresponding need for enhanced parallelism, tighter coherency, and greater bandwidth. RISC-V’s modular ISA offers a scalable solution that accommodates AI compute requirements from intelligent sensors to complex cognitive systems while maintaining architectural consistency.
The landscape of open ISAs is undergoing significant consolidation. Meta’s acquisition of Rivos integrates RISC-V AI server design expertise into one of the largest AI operators, indicating a strategic shift toward proprietary silicon for large language model inference on open architecture. Similarly, GlobalFoundries’ acquisition of MIPS Technologies aligns a previously competing ISA with RISC-V, enhancing foundry-level design support for open-architecture clients and bolstering the supply chain. New entrants like Ahead Computing continue to enrich the ecosystem amidst these consolidations.
Independently, Andes Technology and SiFive remain influential RISC-V intellectual property suppliers, while activity around RISC-V in China is gaining momentum, driven by entities such as Nuclei, Alibaba DAMO Academy, and StarFive. Efforts in Europe, Japan, and China are promoting open ISA initiatives as part of broader technology sovereignty and supply chain resilience strategies, creating a complex landscape where RISC-V’s global openness intersects with national interests in technology.
In summary, RISC-V is transitioning from peripheral roles in control-plane applications to central roles in compute architectures. It does not aim to replace GPUs or proprietary architectures but rather offers a flexible platform for integrating CPUs, vector units, tensor engines, and software-defined accelerators. The market is exploring three primary models: a RISC-V CPU alongside an NPU, a unified compute engine, and compact research-oriented designs sharing resources. Each has its own advantages, and the ongoing developments by companies like GlobalFoundries and Meta signal that RISC-V is becoming a significant player in silicon design. While there is a risk of fragmentation, the flexibility of RISC-V presents a promising avenue for customizing AI hardware without starting from scratch.
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